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| rev. b - jan. 25, 1999 1 preliminary ts80c52x2 8-bit cmos microcontroller 0-60 mhz 1. description temic ts80c52x2 is high performance cmos rom, otp, eprom and romless versions of the 80c51 cmos single chip 8-bit microcontroller. the ts80c52x2 retains all features of the temic 80c51 with extended rom/eprom capacity (8 kbytes), 256 bytes of internal ram, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/ counters. in addition, the ts80c52x2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (euart) and a x2 speed improvement mechanism. the fully static design of the ts80c52x2 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the ts80c52x2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the timers, the serial port and the interrupt system are still operating. in the power-down mode the ram is saved and all other functions are inoperative. 2. features l 80c52 compatible 8051 pin and instruction compatible four 8-bit i/o ports three 16-bit timer/counters 256 bytes scratchpad ram l high-speed architecture 40 mhz @ 5v, 30mhz @ 3v x2 speed improvement capability (6 clocks/ machine cycle) 30 mhz @ 5v, 20 mhz @ 3v (equivalent to 60 mhz @ 5v, 40 mhz @ 3v) l dual data pointer l on-chip rom/eprom (8k-bytes) l programmable clock out and up/down timer/ counter 2 l asynchronous port reset l interrupt structure with 6 interrupt sources, 4 level priority interrupt system l full duplex enhanced uart framing error detection automatic address recognition l low emi (inhibit ale) l power control modes idle mode power-down mode power-off flag l once mode (on-chip emulation) l power supply: 4.5-5v, 2.7-5.5v l temperature ranges: commercial (0 to 70 o c) and industrial (-40 to 85 o c) l packages: pdil40, plcc44, vqfp44 1.4, pqfp f1 (13.9 footprint), cqpj44 (window), cdil40 (window)
2 rev. b - jan. 25, 1999 preliminary ts80c52x2 table 1. memory size 3. block diagram rom (bytes) eprom (bytes) total ram (bytes) ts80c32x2 0 0 256 ts80c52x2 8k 0 256 ts87c52x2 0 8k 256 timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea/v pp psen ale/ xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 (3) (3) c51 core (3) (3) (3) (3) port 0 p0 port 1 port 2 port 3 parallel i/o ports & ext. bus p1 p2 p3 ib-bus reset prog vss vcc (3) (3) (1): alternate function of port 1 (3): alternate function of port 3 timer2 t2ex t2 (1) (1) (2): only available on high pin count packages rom /eprom 8kx8 rev. b - jan. 25, 1999 3 preliminary ts80c52x2 4. sfr mapping the special function registers (sfrs) of the ts80c52x2 fall into the following categories: c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 i/o port registers: p0, p1, p2, p3 timer registers: t2con, t2mod, tcon, th0, th1, th2, tmod, tl0, tl1, tl2, rcap2l, rcap2h serial i/o port registers: saddr, saden, sbuf, scon power and clock control registers: pcon pca registers: cl, ch, ccapil, ccapih, ccon, cmod, ccapmi interrupt system registers: ie, ip, iph others: auxr, ckcon table 2. all sfrs with their address and their reset value bit address- able non bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ffh f0h b 0000 0000 f7h e8h efh e0h acc 0000 0000 e7h d8h dfh d0h psw 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h c7h b8h ip xx00 0000 saden 0000 0000 bfh b0h p3 1111 1111 iph xx00 0000 b7h a8h ie 0x00 0000 saddr 0000 0000 afh a0h p2 1111 1111 auxr1 xxxx 0xx0 a7h 98h scon 0000 0000 sbuf xxxx xxxx 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr xxxxxx00 ckcon xxxx xxx0 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved 4 rev. b - jan. 25, 1999 preliminary ts80c52x2 5. pin configuration p1.7 p1.4 rst p3.0/rxd p3.1/txd p1.3 1 p1.5 p1.6 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0 p2.1 p2.2 p2.3 p2.4 p0.4 p0.6 p0.5 p0.7 ale/prog psen ea/vpp p2.7 p2.5 p2.6 p1.0 p1.2 p1.1 vcc p0.0 p0.1 p0.2 p0.3 pdil/ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 5 4 3 2 1 6 44 43 42 41 40 p1.4 p1.0/t2 p1.1/t2ex p1.3 p1.2 vss1/nic* vcc p0.0/ad0 p0.2/ad2 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea/vpp nic* p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 43 42 41 40 39 44 38 37 36 35 34 p1.4 p1.0/t2 p1.1/t2ex p1.3 p1.2 vss1/nic* vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea/vpp nic* p2.7/a15 p2.5/a13 p2.6/a14 p1.5 p1.6 p1.7 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5 p1.6 p1.7 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.3/ad3 nic* nic* *nic: no internal connection 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 plcc/cqpj 44 33 32 31 30 29 28 27 26 25 24 23 pqfp44 1 2 3 4 5 6 7 8 9 10 11 cdil40 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 vqfp44 rev. b - jan. 25, 1999 5 preliminary ts80c52x2 table 3. pin description for 40/44 pin packages mnemonic pin number type name and function dil lcc vqfp 1.4 v ss 20 22 16 i ground: 0v reference vss1 1 39 i optional ground: contact the sales of?ce for ground connection. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle and power- down operation p0.0-p0.7 39-32 43-36 37-30 i/o port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them ?oat and can be used as high impedance inputs.port 0 pins must be polarized to vcc or vss in order to prevent any parasitic current consumption. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-up when emitting 1s. port 0 also inputs the code bytes during eprom programming. external pull-ups are required during program veri?cation during which p0 outputs the code bytes. p1.0-p1.7 1-8 2-9 40-44 1-3 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. port 1 also receives the low-order address byte during memory programming and veri?cation. alternate functions for port 1 include: 1 2 40 i/o t2 (p1.0): timer/counter 2 external count input/clockout 2 3 41 i t2ex (p1.1): timer/counter 2 reload/capture/direction control p2.0-p2.7 21-28 24-31 18-25 i/o port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr).in this application, it uses strong internal pull-ups emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 sfr. some port 2 pins receive the high order address bits during eprom programming and veri?cation: p2.0 to p2.4 p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. 10 11 5 i rxd (p3.0): serial input port 11 13 7 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 0 13 15 9 i int1 (p3.3): external interrupt 1 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe 17 19 13 o rd (p3.7): external data memory read strobe reset 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc. 6 rev. b - jan. 25, 1999 preliminary ts80c52x2 mnemonic pin number type name and function ale/ pr og 30 33 27 o (i) address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input ( pr og) during eprom programming. ale can be disabled by setting sfrs auxr.0 bit. with this bit set, ale will be inactive during internal fetches. psen 29 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea/v pp 31 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h and 3fffh (rb) or 7fffh (rc), or ffffh (rd). if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 3fffh (rb) or 7fffh (rc) ea must be held low for romless devices. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. if security level 1 is programmed, ea will be internally latched on reset. xtal1 19 21 15 i crystal 1: input to the inverting oscillator ampli?er and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator ampli?er table 3. pin description for 40/44 pin packages rev. b - jan. 25, 1999 7 preliminary ts80c52x2 6. ts80c52x2 enhanced features in comparison to the original 80c52, the ts80c52x2 implements some new features, which are : the x2 option. the dual data pointer. the 4 level interrupt priority system. the power-off flag. the once mode. the ale disabling. some enhanced features are also located in the uart and the timer 2. 6.1 x2 feature the ts80c52x2 core needs only 6 clock periods per machine cycle. this feature called x2 provides the following advantages: l divide frequency crystals by 2 (cheaper crystals) while keeping same cpu power. l save power consumption while keeping same cpu power (oscillator power saving). l save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. l increase cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 compatibility, a divider by 2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by software. 6.1.1 description the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 1. shows the clock generation block diagram. x2 bit is validated on xtal1 ? 2 rising edge to avoid glitches when switching from x2 to std mode. figure 2. shows the mode switching waveforms. figure 1. clock generation diagram xtal1 2 ckcon reg x2 state machine: 6 clock cycles. cpu control f osc f xtal 0 1 xtal1:2 8 rev. b - jan. 25, 1999 preliminary ts80c52x2 figure 2. mode switching waveforms the x2 bit in the ckcon register (see table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature (x2 mode). caution in order to prevent any incorrect operation while operating in x2 mode, user must be aware that all peripherals using clock frequency as time reference (uart, timers) will have their time reference divided by two. for example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. uart with 4800 baud rate will have 9600 baud rate. xtal1:2 xtal1 cpu clock x2 bit x2 mode std mode std mode rev. b - jan. 25, 1999 9 preliminary ts80c52x2 table 4. ckcon register ckcon - clock control register (8fh) reset value = xxxx xxx0b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - - x2 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 x2 cpu and peripheral clock bit clear to select 12 clock periods per machine cycle (std mode, f osc =f xtal / 2). set to select 6 clock periods per machine cycle (x2 mode, f osc =f xtal ). 10 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.2 dual data pointer register ddptr the additional data pointer can be used to speed up code execution and reduce code size in a number of ways. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 5.) that allows the program code to switch between them (refer to figure 3). figure 3. use of dual pointer external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1 rev. b - jan. 25, 1999 11 preliminary ts80c52x2 table 5. auxr1: auxiliary register 1 reset value = xxxx xxx0 not bit addressable application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a source pointer and the other one as a "destination" pointer. 7 6 5 4 3 2 1 0 - - - - - - - dps bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 dps data pointer selection clear to select dptr0. set to select dptr1. 12 rev. b - jan. 25, 1999 preliminary ts80c52x2 assembly language ; block move using dual data pointers ; destroys dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6 jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state. rev. b - jan. 25, 1999 13 preliminary ts80c52x2 6.3 timer 2 the timer 2 in the ts80c52x2 is compatible with the timer 2 in the 80c52. it is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, th2 and tl2, connected in cascade. it is controlled by t2con register (see table 6) and t2mod register (see table 7). timer 2 operation is similar to timer 0 and timer 1. c/ t2 selects f osc /12 (timer operation) or external pin t2 (counter operation) as the timer clock input. setting tr2 allows tl2 to be incremented by the selected input. timer 2 has 3 operating modes: capture, autoreload and baud rate generator. these modes are selected by the combination of rclk, tclk and cp/ rl2 (t2con), as described in the temic 8-bit microcontroller hardware description. refer to the temic 8-bit microcontroller hardware description for the description of capture and baud rate generator modes. in ts80c52x2 timer 2 includes the following enhancements: l auto-reload mode with up or down counter l programmable clock-output 6.3.1 auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 behaves as in 80c52 (refer to the temic 8-bit microcontroller hardware description). if dcen bit is set, timer 2 acts as an up/down timer/counter as shown in figure 4. in this mode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the underflow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. exf2 does not generate any interrupt. this bit can be used to provide 17-bit resolution. 14 rev. b - jan. 25, 1999 preliminary ts80c52x2 figure 4. auto-reload mode up/down counter (dcen = 1) 6.3.2 programmable clock-output in the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (see figure 5) . the input clock increments tl2 at frequency f osc /2. the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers : for a 16 mhz system clock, timer 2 has a programmable frequency range of 61 hz (f osc /2 16) to 4 mhz (f osc /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: l set t2oe bit in t2mod register. l clear c/ t2 bit in t2con register. l determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. l enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or a different one depending on the application. (down counting reload value) c/ t2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt xtal1 : 12 f osc f xtal 0 1 t2conreg t2conreg t2conreg t2conreg t2ex: if dcen=1, 1=up if dcen=1, 0=down if dcen = 0, up counting clock outfrequency C f osc 4 65536 rcap 2 h C rcap 2 l () -------------------------------------------------------------------------------------- = rev. b - jan. 25, 1999 15 preliminary ts80c52x2 l to start the timer, set tr2 run control bit in t2con register. it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. for this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the rcap2h and rcap2l registers. figure 5. clock-out mode c/ t2=0 :2 exf2 tr2 oveflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 xtal1 t2con reg t2con reg t2con reg t2mod reg interrupt qd toggle exen2 16 rev. b - jan. 25, 1999 preliminary ts80c52x2 table 6. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 over?ow flag must be cleared by software. set by hardware on timer 2 over?ow, if rclk = 0 and tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesnt cause an interrupt in up/down counter mode (dcen = 1) 5 rclk receive clock bit clear to use timer 1 over?ow as receive clock for serial port in mode 1 or 3. set to use timer 2 over?ow as receive clock for serial port in mode 1 or 3. 4 tclk transmit clock bit clear to use timer 1 over?ow as transmit clock for serial port in mode 1 or 3. set to use timer 2 over?ow as transmit clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 over?ow. clear to auto-reload on timer 2 over?ows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1. rev. b - jan. 25, 1999 17 preliminary ts80c52x2 table 7. t2mod register t2mod - timer 2 mode control register (c9h) reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - t2oe dcen bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 t2oe timer 2 output enable bit clear to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit clear to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter. 18 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.4 ts80c52x2 serial i/o port the serial i/o port in the ts80c52x2 is compatible with the serial i/o port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as an universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: l framing error detection l automatic address recognition 6.4.1 framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 6). figure 6. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 8.) bit is set. ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control (smod = 0) set fe bit if stop bit is 0 (framing error) (smod = 1) scon (98h) pcon (87h) rev. b - jan. 25, 1999 19 preliminary ts80c52x2 software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 7. and figure 8.). figure 7. uart timings in mode 1 figure 8. uart timings in modes 2 and 3 6.4.2 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the devices address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1 ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1 20 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.4.3 given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains dont-care bits (defined by zeros) to form the devices given address. the dont-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr 0101 0110b saden 1111 1100b given 0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a: saddr 1111 0001b saden 1111 1010b given 1111 0x0xb slave b: saddr 1111 0011b saden 1111 1001b given 1111 0xx1b slave c: saddr 1111 0010b saden 1111 1101b given 1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a dont-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a dont care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 6.4.4 broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as dont-care bits, e.g.: saddr 0101 0110b saden 1111 1100b broadcast =saddr or saden 1111 111xb the use of dont-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a: saddr 1111 0001b saden 1111 1010b broadcast 1111 1x11b, slave b: saddr 1111 0011b saden 1111 1001b broadcast 1111 1x11b, slave c: saddr= 1111 0010b saden 1111 1101b broadcast 1111 1111b for slaves a and b, bit 2 is a dont care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. rev. b - jan. 25, 1999 21 preliminary ts80c52x2 6.4.5 reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all dont-care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. saden - slave address mask register (b9h) reset value = 0000 0000b not bit addressable saddr - slave address register (a9h) reset value = 0000 0000b not bit addressable 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 22 rev. b - jan. 25, 1999 preliminary ts80c52x2 table 8. scon register scon - serial control register (98h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6 sm1 serial port mode bit 1 sm1 sm0 mode description baud rate 0 0 0 shift register f xtal /12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f xtal /64 or f xtal /32 1 1 3 9-bit uart variable 5 sm2 serial port mode 2 bit / multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren reception enable bit clear to disable serial reception. set to enable serial reception. 3 tb8 transmitter bit 8 / ninth bit to transmit in modes 2 and 3. clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8 receiver bit 8 / ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1 ti transmit interrupt ?ag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 ri receive interrupt ?ag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 7. and figure 8. in the other modes. rev. b - jan. 25, 1999 23 preliminary ts80c52x2 table 9. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesnt affect the value of this bit. 7 6 5 4 3 2 1 0 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to to select fe bit in scon register. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode. 24 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.5 interrupt system the ts80c52x2 has a total of 6 interrupt vectors: two external interrupts ( int0 and int1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. these interrupts are shown in figure 9. figure 9. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (see table 11.). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the interrupt priority register (see table 12.) and in the interrupt priority high register (see table 13.). shows the bit values and priority levels associated with each combination. ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high to low priority low priority interrupt global disable individual enable exf2 tf2 ti ri tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 rev. b - jan. 25, 1999 25 preliminary ts80c52x2 table 10. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cant be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 11. ie register ie - interrupt enable register (a8h) reset value = 0x00 0000b bit addressable iph.x ip.x interrupt level priority 0 0 0 (lowest) 0 1 1 1 0 2 1 1 3 (highest) 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 et2 timer 2 over?ow interrupt enable bit clear to disable timer 2 over?ow interrupt. set to enable timer 2 over?ow interrupt. 4 es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3 et1 timer 1 over?ow interrupt enable bit clear to disable timer 1 over?ow interrupt. set to enable timer 1 over?ow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1 et0 timer 0 over?ow interrupt enable bit clear to disable timer 0 over?ow interrupt. set to enable timer 0 over?ow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0. 26 rev. b - jan. 25, 1999 preliminary ts80c52x2 table 12. ip register ip - interrupt priority register (b8h) reset value = xx00 0000b bit addressable 7 6 5 4 3 2 1 0 - - pt2 ps pt1 px1 pt0 px0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 pt2 timer 2 over?ow interrupt priority bit refer to pt2h for priority level. 4 ps serial port priority bit refer to psh for priority level. 3 pt1 timer 1 over?ow interrupt priority bit refer to pt1h for priority level. 2 px1 external interrupt 1 priority bit refer to px1h for priority level. 1 pt0 timer 0 over?ow interrupt priority bit refer to pt0h for priority level. 0 px0 external interrupt 0 priority bit refer to px0h for priority level. rev. b - jan. 25, 1999 27 preliminary ts80c52x2 table 13. iph register iph - interrupt priority high register (b7h) reset value = xx00 0000b not bit addressable 7 6 5 4 3 2 1 0 - - pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 pt2h timer 2 over?ow interrupt priority high bit pt2h pt2 priority le v el 0 0 lowest 01 10 1 1 highest 4 psh serial port priority high bit psh ps priority le v el 0 0 lowest 01 10 1 1 highest 3 pt1h timer 1 over?ow interrupt priority high bit pt1h pt1 priority le v el 0 0 lowest 01 10 1 1 highest 2 px1h external interrupt 1 priority high bit px1h px1 priority le v el 0 0 lowest 01 10 1 1 highest 1 pt0h timer 0 over?ow interrupt priority high bit pt0h pt0 priority le v el 0 0 lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0 priority le v el 0 0 lowest 01 10 1 1 highest 28 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.6 idle mode an instruction that sets pcon.0 causes that to be the last instruction executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirely : the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give and indication if an interrupt occured during normal operation or during and idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the over way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 6.7 power-down mode to save maximum power, a power-down mode can be invoked by software (refer to table 9., pcon register). in power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power-down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 and int1 are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 10. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. in this case the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put ts80c52x2 into power-down mode. figure 10. power-down exit waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase rev. b - jan. 25, 1999 29 preliminary ts80c52x2 table 14. the state of ports during idle and power-down modes * port 0 can force a "zero" level. a "one" will leave port ?oating. mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data* port data port data port data idle external 1 1 floating port data address port data power down internal 0 0 port data* port data port data port data power down external 0 0 floating port data port data port data 30 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.8 once mode (on chip emulation) the once mode facilitates testing and debugging of systems using ts80c52x2 without removing the circuit from the board. the once mode is invoked by driving certain pins of the ts80c52x2; the following sequence must be exercised: l pull ale low while the device is in reset (rst high) and psen is high. l hold ale low as rst is deactivated. while the ts80c52x2 is in once mode, an emulator or test cpu can be used to drive the circuit table 26. shows the status of the port pins during once mode. normal operation is restored when normal reset is applied. table 15. external pin status during once mode ale psen port 0 port 1 port 2 port 3 xtal1/2 weak pull-up weak pull-up float weak pull-up weak pull-up weak pull-up active rev. b - jan. 25, 1999 31 preliminary ts80c52x2 6.9 power-off flag the power-off flag allows the user to distinguish between a cold start reset and a warm start reset. a cold start reset is the one induced by v cc switch-on. a warm start reset occurs while v cc is still applied to the device and could be generated for example by an exit from power-down. the power-off flag (pof) is located in pcon register (see table 16.). pof is set by hardware when v cc rises from 0 to its nominal voltage. the pof can be set or cleared by software allowing the user to determine the type of reset. table 16. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable 7 6 5 4 3 2 1 0 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to to select fe bit in scon register. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 pof power-off flag clear to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode. 32 rev. b - jan. 25, 1999 preliminary ts80c52x2 6.10 reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 17. auxr register auxr - auxiliary register (8eh) reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - extram ao bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 extram extram bit see table 7. 0 ao ale output bit clear to restore ale operation during internal fetches. set to disable ale operation during internal fetches. rev. b - jan. 25, 1999 33 preliminary ts80c52x2 7. ts80c52x2 7.1 rom structure the ts80c52x2 devices are divided in three different arrays: l the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 kbytes. l the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. l the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 7.2 rom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 7.2.1 encryption array within the rom array are 64 bytes of encryption array that are initially unprogrammed (all ffs). every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. this will ensure program protection. 7.2.2 program lock bits the lock bits when programmed according to table 18. will provide different level of protection for the on-chip code and data. u: unprogrammed p: programmed 7.2.3 signature bytes the ts80c52x2 contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section 9. table 18. program lock bits program lock bits protection description security level lb1 lb2 lb3 1 u u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. movc instruction executed from external program memory returns non encrypted data. 2 p u u movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset. 34 rev. b - jan. 25, 1999 preliminary ts80c52x2 8. ts87c52x2 8.1 eprom structure the ts87c52x2 is divided in two different arrays: l the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 kbytes. l the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. in addition a third non programmable array is implemented: l the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 8.2 eprom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 8.2.1 encryption array within the eprom array are 64 bytes of encryption array that are initially unprogrammed (all ffs). every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. this will ensure program protection. 8.2.2 program lock bits the three lock bits, when programmed according to table 19., will provide different level of protection for the on-chip code and data. u: unprogrammed, p: programmed warning: security level 2 and 3 should only be programmed after eprom and core verification. table 19. program lock bits program lock bits protection description security level lb1 lb2 lb3 1 u u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. movc instruction executed from external program memory returns non encrypted data. 2 p u u movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 u p u same as 2, also verify is disabled. 4 u u p same as 3, also external execution is disabled. rev. b - jan. 25, 1999 35 preliminary ts80c52x2 8.2.3 signature bytes the ts80/87c52x2 contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section 9. 8.3 eprom programming 8.3.1 set-up modes in order to program and verify the eprom or to read the signature bytes, the ts87c52x2 is placed in specific set-up modes (see figure 11.). control and program signals must be held at the levels indicated in table 33. 8.3.2 definition of terms address lines: p1.0-p1.7, p2.0-p2.4, p3.4, p3.5 respectively for a0-a12 data lines: p0.0-p0.7 for d0-d7 control signals: rst, psen, p2.6, p2.7, p3.3, p3.6, p3.7. program signals: ale/ prog, ea/vpp. table 20. eprom set-up modes mode rst psen ale/ pr og ea/ vpp p2.6 p2.7 p3.3 p3.6 p3.7 program code data 1 0 12.75v 0 1 1 1 1 verify code data 1 0 1 1 0 0 1 1 program encryption array address 0-3fh 1 0 12.75v 0 1 1 0 1 read signature bytes 1 0 1 1 0 0 0 0 program lock bit 1 1 0 12.75v 1 1 1 1 1 program lock bit 2 1 0 12.75v 1 1 1 0 0 program lock bit 3 1 0 12.75v 1 0 1 1 0 36 rev. b - jan. 25, 1999 preliminary ts80c52x2 figure 11. set-up modes configuration 8.3.3 programming algorithm the improved quick pulse algorithm is based on the quick pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. to program the ts87c52x2 the following sequence must be exercised: l step 1: activate the combination of control signals. l step 2: input the valid address on the address lines. l step 3: input the appropriate data on the data lines. l step 4: raise ea/vpp from vcc to vpp (typical 12.75v). l step 5: pulse ale/ prog once. l step 6: lower ea/vpp from vpp to vcc repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (see figure 12.). 8.3.4 verify algorithm code array verify must be done after each byte or block of bytes is programmed. in either case, a complete verify of the programmed array will ensure reliable programming of the ts87c52x2. p 2.7 is used to enable data output. to verify the ts87c52x2 code the following sequence must be exercised: l step 1: activate the combination of program and control signals. l step 2: input the valid address on the address lines. l step 3: read data on the data lines. repeat step 2 through 3 changing the address for the entire array verification (see figure 12.) +5v vcc p0.0-p0.7 p1.0-p1.7 p2.0-p2.4 vss gnd d0-d7 a0-a7 a8-a12 rst ea/vpp ale/ pr og psen p2.6 p2.7 p3.3 p3.7 p3.6 xtal1 4 to 6 mhz control signals* program signals* * see table 31. for proper value on these inputs rev. b - jan. 25, 1999 37 preliminary ts80c52x2 the encryption array cannot be directly verified. verification of the encryption array is done by observing that the code array is well encrypted. figure 12. programming and verification signals waveform 8.4 eprom erasure (windowed packages only) erasing the eprom erases the code array, the encryption array and the lock bits returning the parts to full functionality. erasure leaves all the eprom cells in a 1s state (ff). 8.4.1 erasure characteristics the recommended erasure procedure is exposure to ultraviolet light (at 2537 ?) to an integrated dose at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. erasure of the eprom begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 ?. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. control signals data in ale/ pr og a0-a12 programming cycle 100 m s d0-d7 ea/vpp data out read/verify cycle 12.75v 5v 0v 38 rev. b - jan. 25, 1999 preliminary ts80c52x2 9. signature bytes the ts80/87c52x2 has four signature bytes in location 30h, 31h, 60h and 61h. to read these bytes follow the procedure for eprom verify but activate the control lines provided in table 31. for read signature bytes. table 33. shows the content of the signature byte for the ts80/87c52x2. table 21. signature bytes content location contents comment 30h 58h manufacturer code: temic 31h 57h family code: c51 x2 60h 2dh product name: ts80c52x2 60h adh product name: ts87c52x2 60h 20h product name: ts80c32x2 61h ffh product revision number rev. b - jan. 25, 1999 39 preliminary ts80c52x2 10. electrical characteristics 10.1 absolute maximum ratings (1) ambiant temperature under bias: c = commercial 0 cto70 c i = industrial -40 cto85 c storage temperature -65 cto+150 c voltage on v cc to v ss -0.5vto+7v voltage on v pp to v ss -0.5vto+13v voltage on any pin to v ss -0.5vtov cc + 0.5 v power dissipation 1 w (2) notes 1. s tresses at or above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is speci?cation is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package. 40 rev. b - jan. 25, 1999 preliminary ts80c52x2 10.2 dc parameters for standard voltage t a =0 cto+70 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. t a = -40 cto+85 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. table 22. dc parameters in standard voltage symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 (6) 0.3 0.45 1.0 v v v i ol = 100 m a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 v v v i ol = 200 m a (4) i ol = 3.2 ma (4) i ol = 7.0 ma (4) v oh output high voltage, ports 1, 2, 3 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 m a i oh = -30 m a i oh = -60 m a v cc = 5 v 10% v oh1 output high voltage, port 0, ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -200 m a i oh = -3.2 ma i oh = -7.0 ma v cc = 5 v 10% r rst rst pulldown resistor 50 90 (5) 200 k w i il logical 0 input current ports 1, 2 and 3 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 -650 m a vin = 2.0 v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current 10 (5) 50 m a 2.0 v < v cc < 5.5 v (3) i cc power supply current (7) freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 3 12 mhz icc op = 1.25 freq (mhz) + 5 ma icc idle = 0.36 freq (mhz) + 2.7 ma (5) 13@12 mhz 16@16mhz 5.5@12mz 7@16 mhz 1.8 1 10 4 ma ma ma ma ma ma v cc = 5.5 v (1) v cc = 5.5 v (2) rev. b - jan. 25, 1999 41 preliminary ts80c52x2 10.3 dc parameters for low voltage t a =0 cto+70 c; v ss =0v;v cc = 2.7 v to 5.5 v 10%;f=0to30 mhz. t a = -40 cto+85 c; v ss =0v;v cc = 2.7 v to 5.5 v 10%;f=0to30 mhz. table 23. dc parameters for low voltage notes 1. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 16.), v il = v ss + 0.5 v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator used.. 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch ,t chcl = 5 ns, v il =v ss + 0.5 v, v ih =v cc - 0.5 v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 14.). 3. power down i cc is measured with all output pins disconnected; ea = v ss , port 0 = v cc ; xtal2 nc.; rst = v ss (see figure 15.). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. 7. for other values, please contact your sales of?ce. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 (6) 0.45 v i ol = 0.8 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.45 v i ol = 1.6 ma (4) v oh output high voltage, ports 1, 2, 3 0.9 v cc v i oh = -10 m a v oh1 output high voltage, port 0, ale, psen 0.9 v cc v i oh = -40 m a i il logical 0 input current ports 1, 2 and 3 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 -650 m a vin = 2.0 v r rst rst pulldown resistor 50 90 (5) 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current tbd (5) tbd m a v cc = 2.0 v to 5.5 v (3) i cc power supply current (7) active mode 16mhz idle mode 16mhz tbd (5) tbd (5) tbd tbd ma ma v cc = 3.3 v (1) v cc = 3.3 v (2) 42 rev. b - jan. 25, 1999 preliminary ts80c52x2 figure 13. i cc test condition, active mode figure 14. i cc test condition, idle mode figure 15. i cc test condition, power-down mode ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. rev. b - jan. 25, 1999 43 preliminary ts80c52x2 figure 16. clock signal waveform for i cc tests in active and idle modes 10.4 ac parameters 10.4.1 explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a =0to+70 c; v ss =0v;v cc =5v 10%; -m and -v ranges. t a = -40 cto+85 c; v ss =0v; v cc =5v 10%; -m and -v ranges. t a =0to+70 c; v ss =0v;2.7v rev. b - jan. 25, 1999 45 preliminary ts80c52x2 table 26. ac parameters for a variable clock 10.4.3 external program memory read cycle figure 17. external program memory read cycle symbol type standard clock x2 clock -m -v -l units t lhll min 2 t - x t - x 10 8 40 ns t avll min t - x 0.5 t - x 15 10 30 ns t llax min t - x 0.5 t - x 15 10 30 ns t lliv max 4 t - x 2 t - x 30 22 75 ns t llpl min t - x 0.5 t - x 15 10 30 ns t plph min 3 t - x 1.5 t - x 15 5 45 ns t pliv max 3 t - x 1.5 t - x 50 25 90 ns t pxix min x x 0 0 0 ns t pxiz max t - x 0.5 t - x 7 5 20 ns t pxav min t - x 0.5 t - x 7 5 20 ns t aviv max 5 t - x 2.5 t - x 40 30 105 ns t plaz max x x 10 10 10 ns t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t aviv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax 46 rev. b - jan. 25, 1999 preliminary ts80c52x2 10.4.4 external data memory characteristics table 27. symbol description symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t av dv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high rev. b - jan. 25, 1999 47 preliminary ts80c52x2 table 28. ac parameters for a fix clock speed (see ordering) -m -v -l units symbol min max min max min max t rlrh 105 85 200 ns t wlwh 105 90 200 ns t rldv 100 60 155 ns t rhdx 0 0 0 ns t rhdz 15 13 40 ns t lldv 160 100 310 ns t av dv 165 100 360 ns t llwl 40 110 30 65 90 60 ns t avwl 40 27 100 ns t qvwx 3 0 18 ns t qvwh 145 90 280 ns t whqx 10 7 20 ns t rlaz 0 0 0 ns t whlh 5 45 5 29 20 80 ns 48 rev. b - jan. 25, 1999 preliminary ts80c52x2 table 29. ac parameters for a variable clock 10.4.5 external data memory write cycle figure 18. external data memory write cycle symbol type standard clock x2 clock -m -v -l units t rlrh min 6 t - x 3 t - x 45 15 100 ns t wlwh min 6 t - x 3 t - x 45 10 100 ns t rldv max 5 t - x 2.5 t - x 25 23 95 ns t rhdx min x x 0 0 0 ns t rhdz max 2 t - x t - x 35 20 60 ns t lldv max 8 t - x 4t -x 40 33 90 ns t av dv max 9 t - x 4.5 t - x 60 50 90 ns t llwl min 3 t - x 1.5 t - x 35 20 60 ns t llwl max 3 t + x 1.5 t + x 35 15 60 ns t avwl min 4 t - x 2 t - x 60 40 100 ns t qvwx min t - x 0.5 t - x 22 17 32 ns t qvwh min 7 t - x 3.5 t - x 30 27 70 ns t whqx min t - x 0.5 t - x 15 10 30 ns t rlaz max x x 0 0 0 ns t whlh min t - x 0.5 t - x 20 12 30 ns t whlh max t + x 0.5 t + x 20 12 30 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh rev. b - jan. 25, 1999 49 preliminary ts80c52x2 10.4.6 external data memory read cycle figure 19. external data memory read cycle 10.4.7 serial port timing - shift register mode table 31. ac parameters for a fix clock table 30. symbol description symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid speed (see ordering) -m -v -l units symbol min max min max min max t xlxl 300 200 600 ns t qvhx 200 117 367 ns t xhqx 20 13 50 ns t xhdx 0 0 0 ns t xhdv 200 117 367 ns ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t av dv t llax 50 rev. b - jan. 25, 1999 preliminary ts80c52x2 table 32. ac parameters for a variable clock 10.4.8 shift register timing waveforms figure 20. shift register timing waveforms symbol type standard clock x2 clock -m -v -l units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 50 133 ns t xhqx min 2 t - x t - x 30 20 50 ns t xhdx min x x 0 0 0 ns t xhdv max 10 t - x 5 t- x 50 50 133 ns valid valid input data valid valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid rev. b - jan. 25, 1999 51 preliminary ts80c52x2 10.4.9 eprom programming and verification characteristics t a =21 cto27 c; v ss = 0v; v cc =5v 10%. 10.4.10 eprom programming and verification waveforms figure 21. eprom programming and verification waveforms table 33. eprom programming parameters symbol parameter min max units v pp programming supply voltage 12.5 13 v i pp programming supply current 75 ma 1/t clcl oscillator frquency 4 6 mhz t av g l address setup to pr og low 48 t clcl t ghax adress hold after pr og 48 t clcl t dvgl data setup to pr og low 48 t clcl t ghdx data hold after pr og 48 t clcl t ehsh (enable) high to v pp 48 t clcl t shgl v pp setup to pr og low 10 ms t ghsl v pp hold after pr og 10 ms t glgh pr og width 90 110 ms t avqv address to valid data 48 t clcl t elqv enable low to data valid 48 t clcl t ehqz data float after enable 0 48 t clcl t ghsl t ehsh ale/prog t av g l t dvgl p0 p1.0-p1.7 p2.0-p2.4 ea/v cc control signals (enable) address data in v cc v pp v cc t ghax t ghdx t glgh t shgl address data out t avqv t elqv t ehqz programming verification 52 rev. b - jan. 25, 1999 preliminary ts80c52x2 10.4.11 external clock drive characteristics (xtal1) 10.4.12 external clock drive waveforms figure 22. external clock drive waveforms 10.4.13 ac testing input/output waveforms figure 23. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic 1 and 0.45v for a logic 0. timing measurement are made at v ih min for a logic 1 and v il max for a logic 0. 10.4.14 float waveforms figure 24. float waveforms table 34. ac parameters symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5 v 0.45 v 0.7v cc 0.2v cc -0.1 v t chcl t clcx t clcl t clch t chcx 0.45 v v cc -0.5 v 0.2v cc +0.9 0.2v cc -0.1 input/output v ol +0.1 v v oh -0.1 v float v load v load +0.1 v v load -0.1 v rev. b - jan. 25, 1999 53 preliminary ts80c52x2 for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 3 20ma. 10.4.15 clock waveforms valid in normal clock mode. in x2 mode xtal2 signal must be changed to xtal2 divided by two. figure 25. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. clock xtal2 ale internal state4 state5 state6 state1 state2 state3 state4 state5 extern al pr ogram memor y fetch read cycle write cycle serial por t shift clock por t opera tion psen p0 p2 (ext) rd p0 p2 p0 p2 wr txd (mode 0) rxd sampled rxd sampled p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled mov dest port (p1, p2, p3) (includes int0, int1, to, t1) mov dest p0 old data new data dpl or rt out data out pcl out (even if program memory is internal) pcl out (if program memory is external) indicates dph or p2 sfr to pch transition dpl or rt out float pcl out (if program memory is external) indicates dph or p2 sfr to pch transition indicates address transitions float float float pcl out pcl out pcl out data sampled data sampled data sampled these signals are not activated during the execution of a movx instruction p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 54 rev. b - jan. 25, 1999 preliminary ts80c52x2 11. ordering information table 35. maximum clock frequency code -m -v -l unit standard mode, oscillator frequency standard mode, internal frequency 40 40 40 40 30 30 mhz x2 mode, oscillator frequency x2 mode, internal equivalent frequency 20 40 30 60 20 40 mhz 87c52x2 packages: a: pdil 40 b: plcc 44 c: pqfp f1 (13.9 mm footprint) e: vqfp 44 (1.4mm) eprom-uv erasable (*) j: window cdil 40* k: window cqpj 44* ts part number 80c32x2: romless 80c52x2: 8k rom 87c52x2: 8k otp temic semiconductors c temperature range c: commercial 0 to 70 o c i: industrial -40 to 85 o c -m conditioning r: tape & reel d: dry pack b: tape & reel and dry pack r (*) check with temic sales of?ce for availability b -m: vcc: 5v +/- 10% 40 mhz, standard mode 20 mhz, x2 mode -v: vcc: 5v +/- 10% 40 mhz, standard mode 30 mhz, x2 mode -l: vcc: 2.7 to 5.5 v 30 mhz, standard mode 20 mhz, x2 mode |
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